Designing Languages to Aid Verification

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• David Pearce (Victoria University of Wellington)
• Friday 27 February 2009, 15:15-16:15
• GS15, Computer Laboratory.

If you have a question about this talk, please contact Boris Feigin.

Automated Software Verification has received considerable attention over the years, with numerous success stories. However, software written in mainstream programming languages is not routinely verified. While some progress has been made on tools for this purpose—most notably ESC /Java and Spec#—they have not seen widespread use. The problem is that mainstream languages are simply not suited to verification. In this talk, I want to examine why this is. In particular, to consider what languages constructs are problematic, and how we might modify them to reduce these effects. The goal is to find small changes to existing languages which offer big improvements.

This talk is part of the Computer Laboratory Programming Research Group Seminar series.

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