University of Cambridge > > Semiconductor Physics > HIGH MOBILITY III-V MOSFET TECHNOLOGY


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In recent years, fundamental interface issues have been overcome and GaAs MOS technology has advanced to the level of device fabrication. This development has been enabled by a molecular beam epitaxy (MBE) deposited Ga2O3 template with the unique property of unpinning the Fermi level on GaAs, and a GdGaO dielectric layer which provides required band offsets while neither disrupting the template nor creating a secondary interface In this invited talk, we will review interface properties and characterization, wafer fabrication, process integration, high mobility transistor design, channel mobility, and transistor data. MOSFET wafers with an InGaAs channel layer have been grown by MBE on III -V substrates including the high-k dielectric Ga2O3/GdGaO stack (k . 20). Electron mobilities exceeding 12,000 and 6,000 cm2/Vs for sheet carrier concentration ns of about 2.5×1012 cm-2 have been measured on InP and GaAs based MOSFET structures, respectively. GaAs based enhancement-mode MOSFE Ts have been manufactured employing a new, implant-free device concept, which allows one to take advantage of high mobility in MOSFET channel layers Transistor data will be presented.

[1] M. Passlack, J. Vacuum Science & Technology B, vol. B23 , no. 4, pp. 1773-1781, 2005.

[2] US Patent 6,963,090

This talk is part of the Semiconductor Physics series.

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