University of Cambridge > Talks.cam > Computer Laboratory Computer Architecture Group Meeting > RISC-V: A Free and Open Instruction Set Architecture

RISC-V: A Free and Open Instruction Set Architecture

Add to your list(s) Download to your calendar using vCal

If you have a question about this talk, please contact Robert Mullins.

RISC -V is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education, but for which we now have grander goals: Just as Linux has become the standard OS for most computing devices, we envision RISC -V becoming the standard ISA for all computing devices.

In this talk, I’ll first present our arguments why instruction sets want to be free, then introduce our motivations in designing a new ISA , give an overview of the RISC -V ISA , and conclude with current status and future plans.

Krste Asanovic is a Professor in the EECS Department at the University of California, Berkeley. He received a B.A. in Electrical and Information Sciences from Cambridge University in 1987 and a Ph.D. in Computer Science from U.C. Berkeley in 1998. He joined the EECS faculty at MIT in 1998, receiving tenure in 2005. Escaping the brutal Boston winters, he moved back to UC Berkeley and co-founded the Berkeley Parallel Computing Laboratory in 2007. He is currently the Director of the ASPIRE Lab, which includes 11 faculty and around 50 graduate students focused on software and hardware specialization for improved energy efficiency. His various research projects have designed and fabricated over a dozen experimental microprocessor prototypes.

This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.

Tell a friend about this talk:

This talk is included in these lists:

Note that ex-directory lists are not shown.

 

© 2006-2020 Talks.cam, University of Cambridge. Contact Us | Help and Documentation | Privacy and Publicity