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CAS FPGA Talks
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FPGA -related talks in the CAS Group at IC If you have a question about this list, please contact: Dr George A Constantinides; Alastair Smith. If you have a question about a specific talk, click on that talk to find its organiser. 0 upcoming talks and 46 talks in the archive. What is Web 2.0 and how it changes almost everything!
TIADC Mismatch Compensation
Parallel Computation of the Phylogenetic Likelihood Kernel in HW and SW
Static scheduling of SDRAM commands using constraint logic programming
FCCM Preview: More FLOPS or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control
MRSC Preview: An FPGA-Based Floating Point Solver for Band Structured Linear Equations
ARC Preview: Word-length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator
ARC Preview: Heterogeneous Architecture Exploration: Analysis vs Parameter Sweep
Challenges in FPGA Research
Multiplication Without Multipliers: Algorithms, Applications, and Extensions
Predicting minimal error bounds through an algorithm
Challenges in FPGA Research
More FLOPS or more precision? Accuracy Parameterizable Linear Equation Solvers for Model-Predictive Control
Fixed-Point Arithmetic in DSP
FPGA architecture optimisation using geometric programming
Transforming image processing algorithms for efficient FPGA implementation
'A linear algebra framework for automatic determination of optimal data layouts' by Mahmut Kandemir et al.
Heterogeneous Architecture Exploration: Analysis vs. Parameter sweep
(FPT Preview) Optimizing Coarse-Grained Units in Floating Point Hybrid FPGAs
(FPT Preview) Modelling and Compensating for Clock Skew Variability in FPGAs
(FPT Preview) A Transition Probability Based Delay Measurement Method for Arbitrary Circuits on FPGAs
(FPT Preview) Co-optimisation of Datapath and Memory in Outer Loop Pipelining
(FPT Preview) A Scalable FPGA Architecture for Non-linear SVM Training
CG: Optimizing FPGA Speed using Custom Precision
Improving Real-time Observability in Embedded Logic Analysis
COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip
On Logical Masking Effects of Soft Errors
A New Approach for Exploring Numerical Accuracy
Wirelength Modeling for Homogeneous and Heterogeneous FPGA Architectural Development
Accelerating Iterative Methods Using FPGAs
Developing analytical techniques for FPGA architecture design
Some Ideas from my Sabbatical
Fault Tolerance and Reliability in FPGAs
Memory and Datapath optimisation for FPGA co-processors
Four Important Concepts to Consider when Using Multicore Clusters
Combining Data Reuse Exploitation with Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework
An FPGA-based Implementation of the MINRES Algorithm
Efficient FPGA Mapping of Gilbert's Algorithm for SVM Training on Large-Scale Classification Problems
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation
Low-Power Design for Reconfigurable Computing
Investigating I/O & Memory Bandwidth trade-offs for Iterative Algorithms’
From the Horse's Mouth - Architecture of Stratix III
Please see above for contact details for this list. |
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Antonio Roldao (PhD@IC).
Thursday 14 May 2009, 14:30-15:30