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Programmable Logic Core Based Post-Silicon Debug For SoCs

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Producing a functionally correct integrated circuit is becoming increasingly difficult. No matter how careful a designer is, there will always be integrated circuits that are fabricated, but do not operate as expected. Providing a means to effectively debug these integrated circuits is vital to help pin-point problems and reduce the number of re-spins required to create a correctly-functioning chip. In this talk, I will show that programmable logic cores (PLCs) and flexible networks can provide this debugging capability. I will elaborate on our PLC based debug infrastructure and summarize our current research. I will address issues such as defining the debug architecture and debug methodology, determining the expected area overhead, optimizing the interconnect topology, creating a high throughput multi-frequency on-chip network and building efficient interfaces between the PLC and fixed-function logic. Finally, I will give some insight into our latest work that combines our debug architecture with formal verification techniques.

This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.

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