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Efficient FPGA Mapping of Gilbert's Algorithm for SVM Training on Large-Scale Classification Problems

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If you have a question about this talk, please contact Dr George A Constantinides .

Support Vector Machines (SVMs) are an effective, adaptable and widely used method for supervised classification. However, training an SVM classifier on large-scale problems is proven to be a very time-consuming task for software implementations. This paper presents a scalable high performance FPGA architecture of Gilbert’s Algorithm on SVM , which maximally utilizes the features of an FPGA device to accelerate the SVM training task for large-scale problems. Initial comparisons of the proposed architecture to the software approach of the algorithm show a speed-up factor range of three orders of magnitude for the SVM training time, regarding a wide range of data’s characteristics.

This talk is part of the CAS FPGA Talks series.

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Cambridge University Engineering Department, Lecture Room 4 Lecture Theatre 1, Department of Chemical Engineering & Biotechnology, New Museum Site, Pembroke Street CB2 3RA Rooms SG1 & SG2, Alison Richard Building, 7 West Road, Cambridge, CB3 9DT

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