Abstract

For the last 30 years, Moore’s law has delivered an exponential growth in the number of transistors on an integrated circuit, enabling higher clock frequencies and better processor performance. However, as transistor sizes have shrunk, the amount of energy consumed by each processor has been increasing steadily. Power is now a first-class design constraint, requiring sophisticated packaging and cooling systems to be provided that can remove the generated heat from the processor. This talk will examine recently-proposed schemes to tackle this energy problem at three different stages in a system’s life cycle: at design, compilation and runtime. It will consider the use of machine learning to design energy-efficient architectures and predict the performance that an optimising compiler can achieve on them. It will also examine a hybrid compilation / runtime scheme that saves energy in the instruction cache through a profile-directed code placement strategy.