Abstract

Tenstorrent build AI/ML hardware accelerators. This session will contain three talks from their team:

1. Thaddeus Fortenberry – RISC -V, ASI Cs and Chiplets and the Future of Automotive: A Tenstorrent Perspective

Thaddeus Fortenberry’s presentation navigates the shifting landscape of autonomous vehicles, spotlighting advancements in next-generation infotainment and onboard networking. At its core lies the RISC -V architecture, an open-source ISA heralding changes in automotive hardware.

2. Ali Ziadi – Graph Native Accelerators for ML

Ali Zaidi will identify the fundamental computational patterns prevalent in ML workloads and examine how conventional systems encounter performance, scaling, and efficiency bottlenecks when dealing with these patterns. Finally, he will spotlight the key features of the Tensix AI Architecture that address these challenges and lay the groundwork for a more future-proof roadmap of ML accelerators.

3. Luke Yen – Scalable RISC -V Processors for AI

Luke Yen’s presentation will highlight our work on developing a disruptive server class RISC -V CPU architecture for AI, data center packet processing, and general-purpose compute. Our design is intended to be highly performant, matching the cutting edge of server-class CPUs in performance while being modular and scalable enough to create derivative designs that cater to a broad spectrum of price/performance design points for various markets and use cases. Luke will also highlight how we’re investing in chiplet technology to achieve modularity, flexibility, and performance scalability in an era of slowing Moore’s Law gains.