Abstract

Work by David Grant, Graeme Smecher, Guy Lemieux (all UBC ) and Rosemary Francis (UCambridge)

FPG As are incredibly flexible devices that can behave as any digital logic circuit, subject to capacity and speed limits. But can a massively parallel processor array (MPPA) behave like any digital logic circuit as well?

In this talk, we will consider how to compile Verilog code for execution in an MPPA . This is essentially a parallel logic simulation engine. By “running” several parallel processes, the MPPA is “emulating” an FPGA . Yes, this is a bit slower (1/10th), but there are some remarkable advantages: CAD runtime or “compiling” is 70x faster, and you can time-multiplex logic resources. The latter feature is very powerful, as you can trade space for execution time, and avoid the harsh capacity limits of traditional FPG As. This could be used to emulate much larger systems on a single MPPA than you can build on a single FPGA . Alternatively, JIT -like compilation speeds and space/time folding allows you to perform late binding of software to hardware functions. This also allows a single binary executable image to run at different performance levels on different-sized MPP As.

This is a practise talk for an upcoming FPT2009 presentation.

About the Speaker

Guy Lemieux is an Associate Professor at The University of British Columbia, where he supervises a small group of students working on FPGA architecture and computing on FPG As. Some of his recent contributions include bit- serial wiring to alleviate bit-parallel datapath congestion, a soft vector processor to accelerate embedded data-parallel tasks rather than painstakingly crafting an RTL accelerator. Guy received 3 degrees at the University of Toronto under the supervision of Profs. David Lewis and Stephen Brown.