Abstract

CASCADE Poster Social

Please join us for a look at some of the cutting-edge research in computer architecture coming out of the Department of Computer Science and Technology with a poster session and light refreshments. We’ll have posters from students and postdocs working in the broad area of computer architecture, where you can browse at your leisure, speak directly to the authors and network with other computer architects whilst enjoying an early evening drink and light snacks in the William Gates Building.

Schedule

15:00 – 16:00 | Compiler Tech Talks

16:00 – 18:00 | Cascade Poster Social

Registration https://www.eventbrite.co.uk/e/cascade-poster-session-and-social-event-tickets-1249170325069

Before the Cascade Poster Social, we are hosting a Compiler Tech Talk with Sean Silva.

A High-Velocity Architecture for MLIR AI Compilers

In this talk we present an MLIR -based compiler architecture that delivers predictable performance for AI workloads. We derive its design from intuitive mental models, and along the way subsume seemingly competing goals of performance, portability, and generality into one concept: velocity (of developing the compiler). Hence we call this a high-velocity compiler architecture. We present this compiler architecture in detail, compare it with the most widespread competing architectural ideas, and connect it with prior art.

Sean Silva

... is a Principal Engineer at Encharge AI, where among other responsibilities he leads the architecture and implementation of the compiler. He previously worked on state-of-the-art AI software and hardware for 7 years at Google and Waymo, including IREE , XLA, Google Edge TPU , and Pixel Visual Core. His humble start in the LLVM community was refactoring TableGen in 2012 which has grown into a decade-long adventure through LLVM , Clang, LLD , and MLIR .

https://www.linkedin.com/in/sean-silva-144b611b5/

Slides: https://gist.github.com/ssilva-encharge/022659297610a763792c45d56dad49e3