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An introduction to Model-Based Design with MATLAB and Simulink focusing on HDL code generation with examples showing:

Algorithm design in MATLAB , Simulink and Stateflow
Generation of bit-true and cycle-accurate synthesiable Verilog and VHDL
Control of the HDL architecture and implementation, including sharing and pipelining for trading off speed and area.
Highlighting of critical paths in the model
Generation of hardware resource utilization estimates
Test bench and cosimulation approaches for rapid verification

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An introduction to Model-Based Design with MATLAB and Simulink focusing on HDL code generation with examples showing:

Algorithm design in MATLAB , Simulink and Stateflow
Generation of bit-true and cycle-accurate synthesiable Verilog and VHDL
Control of the HDL architecture and implementation, including sharing and pipelining for trading off speed and area.
Highlighting of critical paths in the model
Generation of hardware resource utilization estimates
Test bench and cosimulation approaches for rapid verification