Scale-Out Processors

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• Boris Grot, EPFL
• Friday 21 September 2012, 10:00-11:00
• Large lecture theatre, Microsoft Research Ltd, 7 J J Thomson Avenue (Off Madingley Road), Cambridge.

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A growing number of today’s most relevant applications are served online and run in large-scale datacenters characterized by thousands of servers and multi-megawatt power budgets. As Dennard scaling comes to a halt, experts are projecting exponential growth in datacenter power and performance requirements in the coming decade, driven by the rising popularity of the online service model. To efficiently meet the computing needs in the post-Dennard era, datacenters will rely on a new form of ISA – Integration, Specialization, and Approximation.

As a first step toward this post-Dennard ISA , we have developed Scale-Out Processors – a processor design methodology that maximizes performance per TCO on scale-out workloads running in large-scale datacenters. Using a metric of performance density, our methodology facilitates the design of optimal configurations, called pods, of core, cache, and interconnect building blocks. Each pod is a stand-alone server-on-chip, a feature that avoids the expense and complexity of global (i.e., inter-pod) interconnect and coherence support. As I will show, Scale-Out Processors enable higher performance, lower TCO , and better technology scalability over existing design alternatives.

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