University of Cambridge > Talks.cam > Computer Laboratory Computer Architecture Group Meeting > Synopsys Processor Designer - Introduction and demonstration

  Browse A-Z

Log in

University Account External (via Google)

🔐 Log In

Information on

Subscribing to talksdetails Finding a talkdetails Adding a talkdetails Disseminating talksdetails Help and Documentationdetails

ℹī¸ Information

Synopsys Processor Designer - Introduction and demonstration

Download to your calendar using vCal

If you have a question about this talk, please contact David Chisnall .

Note unusual time and venue

Processor Designer is a tool for designing processors. Based on a description of the processor architecture in the LISA language, the tool is able to generate an instruction set simulator, software tools such as linker and assembler, as well as a LLVM based compiler, RTL (vhdl and verilog) and instruction set documentation.

It also comes with a debugger providing insight in the processor internals, as well as in the software running on the processor. This talk will first give a generic introduction to the tool and the LISA language. The second part (starting at around 14:15 to 14:30) consists of a demonstration of the tool.

This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.

This talk is included in these lists:

Note that ex-directory lists are not shown.

Other lists

Hardy Building Room 101 Lecture theatre, Sanger Building Centre for Mathematical Sciences, Meeting Room 3, Clarkson Road, Cambridge

Other talks

Fairy Tales "That's History. That's Truth. I Seen It Myself": T'tc~tsa (Wailaki) and the Enslavement of California Native Americans. Nationalising Oil and Knowledge in Iran: Labour, Decolonisation and Colonial Modernity, 1933–51 Title TBC BSU Seminar: "Response Adaptivity Across Clinical Trials In Portfolios of Biomedical Innovations" Title to be confirmed
 

Š 2006-2025 Talks.cam, University of Cambridge. Contact Us | Help and Documentation | Privacy and Publicity