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NetOS Talklet

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If you have a question about this talk, please contact Ionel Gog.

C/C+11 introduced a memory model and explicit orderings on atomic variables into the C/C+ languages. This allows developers of multithreaded programs on multicore systems to choose between a sequentially consistent or more relaxed memory model, with the former easier to reason about and the latter giving faster programs on modern architectures.

LLVM IR incorporated a C/C++11 compatible memory model in LLVM 3 .0. ARM is the most widespread LLVM -supported architecture with a weak memory model by default, and explicit barriers are provided by the data memory barrier (dmb) instruction. We have found that that LLVM ’s insertion of memory barriers is too aggressive in certain cases and present two machine instruction passes that remove these extra instructions where they can be proven to be redundant. The result is a 40% speedup in the lockless data structure that we profiled. We compare the sequentially consistent implementation with one that makes use of more relaxed acquire and release barriers and demonstrate that the compiler is able to generate the same machine code for both.

This talk will cover the memory model in C/C++11, LLVM IR , and on the hardware and discuss the importance of efficient generation of relaxed memory semantics for scalable multithreaded code. We will present our optimisations and propose future directions for improving LLVM ’s code generation on weakly ordered architectures.

This talk is part of the Computer Laboratory NetOS Group Talklets series.

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