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Prof Yu Zhibin, Shenzhen Institutes of Advanced Technology
Tuesday 02 August 2016, 14:00-14:45
Barrier-Aware Warp Scheduling for Throughput Processors
â ī¸ Important: Note unusual time
- đ¤ Speaker: Prof Yu Zhibin, Shenzhen Institutes of Advanced Technology
- đ Date & Time: Tuesday 02 August 2016, 14:00 - 14:45
- đ Venue: Lecture Theatre 1, Computer Laboratory
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Simon Moore
Abstract
Abstract not available
Series This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.
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