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SUMMARY:G: A high-level packet processing language with a high-speed FPGA-
 based implementation - Gordon Brebner\, Xilinx Research Labs
DTSTART:20080905T130000Z
DTEND:20080905T140000Z
UID:TALK13311@talks.cam.ac.uk
CONTACT:Robert Mullins
DESCRIPTION:As the Internet evolves\, it is becoming increasingly necessar
 y to provide multiple packet processing solutions\, in order to support di
 versity and innovation both in services and in underlying infrastructure. 
  In turn\, there is a requirement for supplying underlying high-performanc
 e network node architectures that support flexibility\, scalability\, conc
 urrency\, and diversity.  This talk will discuss modern Field Programmable
  Gate Array (FPGA) devices as a natural technology for the necessary high-
 speed programmable packet processing nodes. It will introduce G\, an exper
 imental high-level packet-centric language for describing packet processin
 g specifications in an implementation-independent manner.  G can be compil
 ed to give high-speed FPGA-based components that can be assembled alongsid
 e other components to build network nodes\, framework based on the MIT Cli
 ck modular approach.  Compilation involves generating virtual processing a
 rchitectures tailored to specific packet processing requirements.  Some ex
 amples (including MPLS and carrier Ethernet) will be presented to illustra
 te the performance obtainable from G solutions\, and the ease of experimen
 tation with both packet processing requirements and implementation charact
 eristics.  The results to date indicate that FPGA devices can be programme
 d in a high-level manner attractive to the networking specialist\, without
  seriously compromising their raw capabilities.\n
LOCATION:SS03\, Computer Laboratory\, William Gates Building
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