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SUMMARY:FPGA's NoC Freedom: You bought it\, so why not use it - Prof Lesle
 y Shannon\, Simon Fraser University
DTSTART:20090213T150000Z
DTEND:20090213T160000Z
UID:TALK16988@talks.cam.ac.uk
CONTACT:Simon Moore
DESCRIPTION:   As high performance systems scale to 10s and 100s of nodes\
 non a single die\, Network-on-Chip (NoC) implementations allow\nmore effec
 tive scaling of performance.  Initially\, NoCs\ntopologies were only used 
 for designs in ASIC technology.\nNow the largest commercial FPGAs can also
  implement\nsystems with more than 100 processing nodes\, making NoC\ntopo
 logies an essential consideration for high performance\ndesigns.  However\
 , FPGAs and ASICs are different technologies.\nASICs are customized to an 
 application\, including only those\nresources that are actually required f
 or the system.  FPGAs\, on\nthe other hand have fixed resources available 
 that exist\nindependent of their usage in the final design.\n   This talk 
 will present results from our current work to\nquantify how the fixed rout
 ing resources of an FPGA affects\nthe freedom of a designer to create an a
 pplication-specific\ntopology for their system that may improve performanc
 e over\ntraditional topologies.  The results presented here will\ninclude 
 effects on routability and performance from variables\nsuch as:\n- the num
 ber and size of nodes in the system\n- the node degree\n- the communicatio
 n link size\n- the device architecture\n- and homogeneous versus heterogen
 eous network nodes\n\n
LOCATION:SS03\, Computer Laboratory\, William Gates Building
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