BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Talks.cam//talks.cam.ac.uk// X-WR-CALNAME:Talks.cam BEGIN:VEVENT SUMMARY:Model Checking: Model Checking for Hardware Design: Where do we st and? - Ziiyad Hanna (University of Oxford) DTSTART:20220722T154500Z DTEND:20220722T163000Z UID:TALK176753@talks.cam.ac.uk DESCRIPTION:Model checking is a widely used technology to verify chip desi gn\, which is at the heart of many areas including handheld devices\, comp uter servers and cloud computing\, mobile phones\, Artificial Intelligence \, AR/VR\, Internet-of-things\, automotive and variety of embedded systems . \; Verification and software bring up consume over 70% of the total cost\, and therefore the industry is consistently looking for solutions to address productivity gaps and cost reduction. Formal Verification and mod el checking in particular play a significant role \; to boost \;ve rification \;productivity and enables many domains in the chip design and implementation cycles including functional\, safety and security verif ication\, logic optimization at various levels of design abstractions star ting from architectural levels down to implementation for both software an d hardware models. In this talk\, we will show how the industry explores a nd exploits various techniques in model checking to make it a practical an d scalable technology\, including key technological and methodological inf lection points that made significant innovations and managed to boost form al. \; Despite the impressive industrial advancements and successful a pplications of model checking technologies for chip design\, it is still v ery young. In this talk we are interested in inspiring the academic commun ity and accelerating research in key challenges through a joint and focuse d research with the industry. The intent is to boost core model checking a lgorithms and abstraction research\, as well as model checking application s to boost the pace of innovation in model checking.\nDr. Ziyad Hanna is a Corporate Vice President of Cadence Design Systems\, and the R&D General Manager of Cadence Israel\, leading the company&rsquo\;s technology innova tions and business in the area of Electronic Design Automation with focus on software verification technologies and solutions for the worldwide chip design industry. Prior to that\, he was the Sr. Vice President and Genera l Manager of Jasper Israel the first startup company that made its way to exit and managed by an Arab Israeli General Manager. Prior to joining Jasp er\, Ziyad was a senior principal engineer and senior manager at Intel in Israel and the US. A senior IEEE member\, Ziyad is very active in the Hi-T ech field and has participated in many international conferences and works hops. He has published more than 30 articles\, has 15 patents\, and gave h undreds of talks in various fields in computer science. Ziyad received num erous awards including Intel's highest achievement award twice\, and Caden ce move-the-needle award. He obtained his bachelor&rsquo\;s and master&rsq uo\;s degree from Tel Aviv University\, and PhD in computer science from O xford University in England\, where he serves as a visiting professor in t he computer science department. Ziyad is very active in fostering the Hi-T ech in the Arab community in Israel and serves as Co-Chair of the General Council of the Tsofen foundation for the development of Hi-Tech in the Ara b community in Israel. Ziyad was ranked number 39 in The Marker&rsquo\;s 1 00 most influential people on the Israel life for year 2019\, also top the list in the Hi-Tech category. Also\, his name was included in the list of the most influential people in Hi-Tech for 2020 in the People and Compute rs magazine. LOCATION:Seminar Room 2\, Newton Institute END:VEVENT END:VCALENDAR