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SUMMARY:Modern Cache Prefetching and Page Size Aware Cache Prefetching - T
 exas A&M
DTSTART:20230913T123000Z
DTEND:20230913T133000Z
UID:TALK205177@talks.cam.ac.uk
CONTACT:Prof Simon Moore
DESCRIPTION:The increase in working set sizes of contemporary\napplication
 s outpaces the growth in cache sizes\, resulting in frequent\nmain memory 
 accesses that deteriorate system performance due to the\ndisparity between
  processor and memory speeds. Prefetching data blocks\nahead of demand acc
 esses has proven successful at attenuating this\nbottleneck. However\, pre
 fetchers operating in the physical address\nspace leave significant perfor
 mance on the table by limiting their\npattern detection within 4KB physica
 l page boundaries when modern\nsystems use page sizes larger than 4KB to m
 itigate the address\ntranslation overheads.\n\nIn this talk I first will d
 iscuss the design and operation of the\nsignature-path prefetcher (SPP)\, 
 the baseline prefetcher for this work\nthat is representative of the prefe
 tchers seen in many current\nmid-to-last level cache designs in industry. 
 Then\, I will use this as\na basis for discussing the exploitation of the 
 high usage of large\npages in modern systems to increase the effectiveness
  of spatial cache\nprefetching.  I will explore the design of Page Size Aw
 are (PSA)\nprefetchers which leverage large page sizes through a\nmicroarc
 hitectural scheme that propagates the page size information to\nthe lower-
 level cache prefetchers\, thus enabling the prefetcher's meta\ndata to be 
 managed at the actual size of the page the data resides in.\nOur scheme en
 ables safe prefetching beyond 4KB physical page\nboundaries when the acces
 sed blocks reside in large pages.  We show\nthat our scheme for page-size 
 awareness is compatible with any cache\nprefetcher without implying design
  modifications.  Interestingly\, we\nfind that in several cases\, even whe
 n data lies in large pages\, its\nsometimes best to manage the prefetcher 
 state at a 4KB boundary\, thus\nwe introduce a set dueling technique to de
 termine the ideal metadata\npage size for a given workload.  Our evaluatio
 n shows that our\nproposals improve single-core geomean performance by an 
 average of\n8.1% (up to 90% for some workloads) over the original implemen
 tation\nof the considered prefetchers\, across 80 memory-intensive workloa
 ds.\n\nBio: Paul V. Gratz is a Professor in the department of Electrical a
 nd\nComputer Engineering at Texas A&M University.  His research interests\
 ninclude efficient and reliable design in the context of high\nperformance
  computer architecture\, processor memory systems and\non-chip interconnec
 tion networks.  He received his B.S. and\nM.S. degrees in Electrical Engin
 eering from The University of Florida\nin 1994 and 1997 respectively.  Fro
 m 1997 to 2002 he was a design\nengineer with Intel Corporation.  He recei
 ved his Ph.D. degree in\nElectrical and Computer Engineering from the Univ
 ersity of Texas at\nAustin in 2008.  His paper\, "Synchronized Progress in
  Interconnection\nNetworks (SPIN) : A New Theory for Deadlock Freedom\," w
 as selected as\na Top Pick from the architecture conferences in 2018 by IE
 EE\nMicro. His papers "Path Confidence based Lookahead Prefetching" and\n"
 B-Fetch: Branch Prediction Directed Prefetching for\nChip-Multiprocessors"
  were nominated for best papers at MICRO '16 and\nMICRO '14 respectively. 
  At ASPLOS '09\, Dr. Gratz received a best\npaper award for "An Evaluation
  of the TRIPS Computer System."  In 2016\nhe received the "Distinguished A
 chievement Award in Teaching – College\nLevel" from the Texas A&M Associ
 ation of Former Students and in 2017\nhe received the "Excellence Award in
  Teaching\, 2017" from the Texas\nA&M College of Engineering.
LOCATION:Lecture Theatre 2\, Department of Computer Science & Technology\,
  15 JJ Thompson Avenue\, Madingley Road\, Cambridge\, CB3 0FD
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