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SUMMARY:Proximity Coherence for Chip Multiprocessors: A communication-cent
 ric cache coherency protocol extension - Nick Barrow-Williams
DTSTART:20091028T163000Z
DTEND:20091028T173000Z
UID:TALK21179@talks.cam.ac.uk
CONTACT:Simon Moore
DESCRIPTION:We propose Proximity Coherence\, a scheme in which L1 load mis
 ses are optimistically forwarded to nearby caches via dedicated links rath
 er than always being indirected via a directory structure. Such an optimiz
 ation is enabled by the comparable cost of local cache accesses with the u
 se of on-chip network resources. Coherency is maintained through the use o
 f lightweight graph structures embedded in the L1 caches.
LOCATION:SS03\, Computer Laboratory\, William Gates Building
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