BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Talks.cam//talks.cam.ac.uk//
X-WR-CALNAME:Talks.cam
BEGIN:VEVENT
SUMMARY:Exposing Fine-grain Concurrency in Sequential code with a Dataflow
  Compiler IR - Ali Mustafa Zaidi (University of Cambridge)
DTSTART:20130604T130000Z
DTEND:20130604T134500Z
UID:TALK45674@talks.cam.ac.uk
CONTACT:Prof Simon Moore
DESCRIPTION:Despite the move towards increasingly parallel computer\narchi
 tectures\, achieving high single-thread performance remains\ncritical for 
 improving overall speed-up. Unfortunately\, the only\nway of achieving goo
 d sequential performance today is with power\nhungry superscalar processor
 s. Yet\, with the impending dark\nsilicon problem severely limiting multic
 ore performance scaling\,\nthere is an ever increasing need for architectu
 res that provide\nhigh energy efficiency. This leaves designers with a zer
 o sum\ntrade-off: application speed-ups will be limited either by\npoor (b
 ut energy efficient) sequential performance\, or by limited\npower budgets
  leading to more dark silicon.\n \nThis talk describes research work aimed
  at understanding and\nexpanding the design space for computer architectur
 e when\nimplementing sequential code. A new compiler IR is developed\nthat
  (a) statically exposes fine-grained concurrency (ILP) in\nsequential\, co
 ntrol-flow intensive code\, and (b) can be\nimplemented as dataflow custom
  hardware to maximize energy\nefficiency. To test the IR\, a high-level sy
 nthesis tool-chain is\nimplemented to compile code to custom hardware. Fro
 m this\, we\npresent area\, energy and performance results. Additional wor
 k is\nproposed where the IR would allow sequential applications to be\nimp
 lemented on 'composable' architectures\, where multiple simple\ncores are 
 combined to accelerate sequential software.\n
LOCATION:SS03\, Computer Laboratory
END:VEVENT
END:VCALENDAR