Robert Mullins

Name:	Robert Mullins
Affiliation:	University of Cambridge
E-mail:	(only provided to users who are logged into talks.cam)
Last login:	Fri Jan 12 13:46:41 +0000 2024

Public lists managed by Robert Mullins

• Computer Laboratory Computer Architecture Group Meeting
• Hardware for Machine Learning

Talks given by Robert Mullins

Obviously this only lists talks that are listed through talks.cam. Furthermore, this facility only works if the speaker's e-mail was specified in a talk. Most talks have not done this.

Talks organised by Robert Mullins

This list is based on what was entered into the 'organiser' field in a talk. It may not mean that Robert Mullins actually organised the talk, they may have been responsible only for entering the talk into the talks.cam system.

• SQuadS: Self-Serve System Services for new Hardware-Software Cooperation
• Tenstorrent - building AI/ML accelerators
• Deploying Deep Neural Networks in the Embedded Space
• Hardware for Neural Networks
• Redundancy in Deep Neural Networks and Its Impacts to Hardware Accelerator Design
• The Biomaker Challenge: an introduction
• Processors for the Data Center and Cloud of the Future
• The Future of Computer Architecture
• OpenPiton
• Harder, Better, Faster, Stronger - Elliptic Curve Discrete Logarithm Computations on FPGAs
• Bringing computer vision to the masses
• RISC-V: A Free and Open Instruction Set Architecture
• The New Cambridge Phenomenon?
• Scale-Out Processors
• An Energy-Efficient Patchable Accelerator For Post-Silicon Engineering Changes
• RISC Instructions for Capability Acceleration
• LiquidMetal: a unified programming language and runtime for heterogeneous platforms
• Spatial Computation
• Kiwi HLS (high-level synthesis) - C# programs with FPGA acceleration
• Stream Chaining: Exploiting Multiple Levels of Correlation in Data Prefetching
• The Berkeley Parallel Computing Laboratory
• Link-Time Optimization for Instruction Cache Power Efficiency
• Design, Compilation and Runtime Solutions for Energy-Efficient Microprocessors
• Two generations of Many-Core Computational Arrays
• G: A high-level packet processing language with a high-speed FPGA-based implementation