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Flow-Aware Allocation for On-Chip Networks

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If you have a question about this talk, please contact Prof Simon Moore .

Note unusual time and venue

Current Virtual-Channel routers disregard potentially useful information about on-chip communication flows. This often leads to inefficient resource utilisation in existing Networks-on-Chips for flow-based communication patterns. The flow-based traffic exhibited by forthcoming applications requiring large streaming datasets (sophisticated graphical interfaces, mobile connectivity, scientific applications, etc.) lead us to propose flow additions to a Virtual-Channel network. Our flow-based refinements infer the presence of, and allocate resources to flows rather than individual packets. As a consequence, we are able to demonstrate speedups of close to 40% for synthetic flow-based traffic patterns.

This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.

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FW11 Seminar Room (William Gates Building) Room GS1, Donald McIntyre Building, Faculty of Education, 184 Hills Road, Cambridge Cambridge University Engineering Department, TBD

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