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Proximity Coherence for Chip Multiprocessors: A communication-centric cache coherency protocol extension

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We propose Proximity Coherence, a scheme in which L1 load misses are optimistically forwarded to nearby caches via dedicated links rather than always being indirected via a directory structure. Such an optimization is enabled by the comparable cost of local cache accesses with the use of on-chip network resources. Coherency is maintained through the use of lightweight graph structures embedded in the L1 caches.

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