Abstract

Abstract: We will explore a couple of topics of recent interest to me: how to best bridge the Boolean world of hardware design with the continuous world of modern machine learning, and how to utilise recent advances in graph rewriting for datapath optimization. The former will lead us to explore how the fundamental computational units of deep learning might be reconsidered with hardware efficiency in mind. The latter will allow us to optimize hardware for computer arithmetic, including automated (re-)discovery of well-known manual tricks, and is now in use by Intel. This talk summarises the outcomes of joint work with Marta Andronic, Peter Cheung, Sam Coward, James Davis, Theo Drane and Erwei Wang.

Bio: George A. Constantinides received the Ph.D. degree from Imperial College London in 2001. Since 2002, he has been with the faculty at Imperial College London, where he is currently Professor of Digital Computation and Director of the Imperial Early Career Researcher Institute, having previously served as Associate Dean of Engineering and Head of Circuits and Systems. He has been TPC chair of the FPGA , FPL and FPT conferences. He currently serves on several program committees and has published over 200 research papers in peer refereed journals and international conferences. Prof Constantinides enjoys family, espresso and general geekery.

Link to join virtually: https://cam-ac-uk.zoom.us/j/87421957265

A recording of this talk is available at the following link: https://www.cl.cam.ac.uk/seminars/wednesday/video/

This talk is being recorded. If you do not wish to be seen in the recording, please avoid sitting in the front three rows of seats in the lecture theatre. Any questions asked will also be included in the recording. The recording will be made available on the Department’s webpage

This Wednesday Seminar will be followed by a Compiler Social. Please find further information and registration details at the following link: https://grosser.science/compiler-social-2025-02-12/