Abstract

Despite the move towards increasingly parallel computer architectures, achieving high single-thread performance remains critical for improving overall speed-up. Unfortunately, the only way of achieving good sequential performance today is with power hungry superscalar processors. Yet, with the impending dark silicon problem severely limiting multicore performance scaling, there is an ever increasing need for architectures that provide high energy efficiency. This leaves designers with a zero sum trade-off: application speed-ups will be limited either by poor (but energy efficient) sequential performance, or by limited power budgets leading to more dark silicon.

This talk describes research work aimed at understanding and expanding the design space for computer architecture when implementing sequential code. A new compiler IR is developed that (a) statically exposes fine-grained concurrency (ILP) in sequential, control-flow intensive code, and (b) can be implemented as dataflow custom hardware to maximize energy efficiency. To test the IR, a high-level synthesis tool-chain is implemented to compile code to custom hardware. From this, we present area, energy and performance results. Additional work is proposed where the IR would allow sequential applications to be implemented on ‘composable’ architectures, where multiple simple cores are combined to accelerate sequential software.